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DATA SHEET
SAA7104E; SAA7105E Digital video encoder
Product specification 2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 8 8.1 8.2 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder RGB processor Triple DAC HD data path Timing generator Pattern generator for HD sync pulses I2C-bus interface Power-down modes Programming the SAA7104E; SAA7105E Input levels and formats Bit allocation map I2C-bus format Slave receiver Slave transmitter BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes 9 10 11 11.1 12 12.1 12.2 12.3 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18
SAA7104E; SAA7105E
LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS Teletext timing APPLICATION INFORMATION Reconstruction filter Analog output voltages Suggestions for a board layout PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
1 FEATURES
SAA7104E; SAA7105E
* Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC * Supports Intel(R) Digital Video Out (DVO) low voltage interfacing to graphics controller * 27 MHz crystal-stable subcarrier generation * Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip or from external source * Programmable assignment of clock edge to bytes (in double edged mode) * Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as reference clock for the VGC, as well) * PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible) * Hot-plug detection through dedicated interrupt pin * Supported VGA resolutions for PAL or NTSC legacy video output up to 1280 x 1024 graphics data at 60 or 50 Hz frame rate * Supported VGA resolutions for HDTV output up to 1920 x 1080 interlaced graphics data at 60 or 50 Hz frame rate * Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) at 27 MHz sample rate (signals in parenthesis are optionally), all at 10-bit resolution * Non-interlaced CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling * Downscaling and upscaling from 50 to 400% * Optional interlaced CB-Y-CR input of Digital Versatile Disk (DVD) signals * Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz) * 3 x 256 bytes RGB Look-Up Table (LUT) * Support for hardware cursor * HDTV up to 1920 x 1080 interlaced and 1280 x 720 progressive, including 3-level sync pulses
(1) MacrovisionTM is a trademark of the Macrovision Corporation.
* Programmable border colour of underscan area * Programmable 5 line anti-flicker filter * On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) * Fast I2C-bus control port (400 kHz) * Encoder can be master or slave * Adjustable output levels for the DACs * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * Internal Colour Bar Generator (CBG) * Optional support of various Vertical Blanking Interval (VBI) data insertion * MacrovisionTM(1) Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to the SAA7104E only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. * Optional cross-colour reduction for PAL and NTSC CVBS outputs * Power-save modes * Joint Test Action Group (JTAG) boundary scan test * Monolithic CMOS 3.3 V device, 5 V tolerant I/Os.
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
2 GENERAL DESCRIPTION
SAA7104E; SAA7105E
When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 x 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port can provide Y, PB and PR signals for HDTV monitors. The device includes a sync/clock generator and on-chip DACs. All inputs intended to interface to the host graphics controller are designed for low-voltage signals between down to 1.1 V and up to 3.6 V.
The SAA7104E; SAA7105E is an advanced next-generation video encoder which converts PC graphics data at maximum 1280 x 1024 resolution (optionally 1920 x 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output. Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors. 3 QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL ILElf(DAC) DLElf(DAC) Tamb 4 PARAMETER analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels
MIN. 3.15 3.15 1 1 - - - - 0
TYP. 3.3 3.3 110 175 1.23 37.5 - - -
MAX. 3.45 3.45 115 200 - - 3 1 70 V V
UNIT
mA mA V LSB LSB C
TTL compatible
analog CVBS output signal voltage for a 100/100 colour bar at 75/2 load (peak-to-peak value) load resistance low frequency integral linearity error of DACs low frequency differential linearity error of DACs ambient temperature
ORDERING INFORMATION PACKAGE
TYPE NUMBER NAME SAA7104E SAA7105E BGA156 DESCRIPTION plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm VERSION SOT472-1
2004 Mar 04
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VDDA1 VDDA2 B6 VDDA3 D6 VDDA4 B6 VSSA1 B8 VSSA2 A8 VDDD1 F4 VDDD2 D4 VDDD3 D4 VDDD4 D4 VSSD1 VSSD2 VSSD3 VSSD4 C5, D5, E4 A4 A7, B7 FIFO + UPSAMPLING LUT + CURSOR RGB TO Y-CB-CR MATRIX A9 B5 D1 DECIMATOR 4 : 4 : 4 to 4:2:2 D3 HORIZONTAL SCALER VERTICAL SCALER VERTICAL FILTER E1 TRST DUMP RSET TDI TDO TMS TCK A10, B9, C9, D9 C5, D5, C5, D5, E4 E4 C5, D5, E4 PD11 to PD0 C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 INPUT FORMATTER PIXCLKI F2
5
Philips Semiconductors
Digital video encoder
BLOCK DIAGRAM
5 5
FIFO BORDER GENERATOR VIDEO ENCODER TRIPLE DAC
C6 C7 C8
BLUE_CB_CVBS GREEN_VBS_CVBS RED_CR_C_CVBS
SAA7104E SAA7105E
G4 PIXEL CLOCK SYNTHESIZER CRYSTAL OSCILLATOR A5 XTALI A6 XTALO FSVGC 27 MHz TTX_SRES CBO C3 TIMING GENERATOR G1 F1 G3 E3
HD OUTPUT D7 I2C-BUS CONTROL C4 G2 E2 D2 D8 F12 VSM HSM_CSYNC
PIXCLKO
SAA7104E; SAA7105E
TVD
mhc572
TTXRQ_XCLKO2
SDA
SCL RESET
VSVGC HSVGC
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital video encoder
6 PINNING SYMBOL PD7 PD4 TRST XTALI XTALO DUMP VSSA2 RSET VDDA1 PD9 PD8 PD5 PD6 TDI VDDA2 VDDA4 VSSA1 PD11 PD10 TTX_SRES TTXRQ_XCLKO2 VSSD1 VSSD2 VSSD3 VSSD4 BLUE_CB_CVBS GREEN_VBS_CVBS RED_CR_C_CVBS TDO RESET TMS VDDD2 VDDD3 VDDD4 VDDA3 PIN A2 A3 A4 A5 A6 A7, B7 A8 A9 A10, B9, C9, D9 B1 B2 B3 B4 B5 B6 B6 B8 C1 C2 C3 C4 C5, D5, E4 C5, D5, E4 C5, D5, E4 C5, D5, E4 C6 C7 C8 D1 D2 D3 D4 D4 D4 D6 TYPE(1) I I I/pu I O O S O S I I I I I S S S I I I O S S S S O O O O I I/pu S S S S
SAA7104E; SAA7105E
DESCRIPTION MSB with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment MSB - 3 with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment test reset input for BST; active LOW; notes 2, 3 and 4 crystal oscillator input crystal oscillator output DAC reference pin; connected via 12 resistor to analog ground analog ground 2 DAC reference pin; connected via 1 k resistor to analog ground (do not use capacitor in parallel with 1 k resistor) analog supply voltage 1 (3.3 V for DACs) see Tables 9 to 14 for pin assignment see Tables 9 to 14 for pin assignment MSB - 2 with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment MSB - 1 with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment test data input for BST; note 2 analog supply voltage 2 (3.3 V for DACs) analog supply voltage 4 (3.3 V) analog ground 1 see Tables 9 to 14 for pin assignment see Tables 9 to 14 for pin assignment teletext input or sync reset input teletext request output or 13.5 MHz clock output of the crystal oscillator; note 5 digital ground 1 digital ground 2 digital ground 3 digital ground 4 analog output of BLUE or CB or CVBS signal analog output of GREEN or VBS or CVBS signal analog output of RED or CR or C or CVBS signal test data output for BST; note 2 reset input; active LOW test mode select input for Boundary Scan Test (BST); note 2 digital supply voltage 2 (3.3 V for I/Os) digital supply voltage 3 (3.3 V for core) digital supply voltage 4 (3.3 V for core) analog supply voltage 3 (3.3 V for oscillator)
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
SYMBOL VSM HSM_CSYNC TCK SCL HSVGC reserved VSVGC PIXCLKI PD3 VDDD1 TVD FSVGC SDA CBO PIXCLKO PD2 PD1 PD0 Notes
PIN D7 D8 E1 E2 E3 E12 F1 F2 F3 F4 F12 G1 G2 G3 G4 H1 H2 H3
TYPE(1) O O I/pu I I/O - I/O I I S O I/O I/O I/O O I I I
DESCRIPTION vertical synchronization output to monitor (non-interlaced auxiliary RGB) horizontal synchronization output to monitor (non-interlaced auxiliary RGB) or composite sync for RGB-SCART test clock input for BST; note 2 I2C-bus serial clock input horizontal synchronization output to VGC (optional input); note 5 to be reserved for future applications vertical synchronization output to VGC (optional input); note 5 pixel clock input (looped through) MSB - 4 with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment digital supply voltage 1 for pins PD11 to PD0, PIXCLKI, PIXCLKO, FSVGC, VSVGC, HSVGC, CBO and TVD interrupt if TV is detected at DAC output frame synchronization output to Video Graphics Controller (VGC) (optional input); note 5 I2C-bus serial data input/output composite blanking output to VGC; active LOW; note 5 pixel clock output to VGC MSB - 5 with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment MSB - 6 with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment MSB - 7 with CB-Y-CR 4 : 2 : 2; see Tables 9 to 14 for pin assignment
1. Pin type: I = input, O = output, S = supply, pu = pull-up. 2. In accordance with the "IEEE1149.1" standard the pins TDI, TMS, TCK and TRST are input pins with an internal pull-up resistor and TDO is a 3-state output pin. 3. For board design without boundary scan implementation connect TRST to ground. 4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 5. The pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.
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Philips Semiconductors
Product specification
Digital video encoder
Table 1 1 A B PD9 Pin assignment (top view) 2 PD7 PD8 3 PD4 PD5 4 TRST PD6 5 6 7 8 9
SAA7104E; SAA7105E
10
11
12
13
14
XTALI XTALO DUMP TDI VDDA2 VDDA4 DUMP
VSSA2 RSET VDDA1 VSSA1 VDDA1
C PD11
PD10
TTX_ TTXRQ_ VSSD1 BLUE_ GREEN_ RED_ VDDA1 SRES XCLKO2 VSSD2 CB_ VBS_ CR_ VSSD3 CVBS CVBS C_ VSSD4 CVBS TMS VDDD2 VDDD3 VDDD4 VSSD1 VDDA3 VSSD2 VSSD3 VSSD4 VSM HSM_ VDDA1 CSYNC
D
TDO RESET
E
TCK
SCL
HSVGC VSSD1 VSSD2 VSSD3 VSSD4 VDDD1
reserved
F VSVGCPIXCLKI PD3 G FSVGC SDA H J K L M N P PD2 PD1
TVD
CBO PIXCLKO PD0
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
MHC566
handbook, halfpage
P N M L K J H G F E D C B A
SAA7104E SAA7105E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Fig.2 Pin configuration.
7
FUNCTIONAL DESCRIPTION
The digital video encoder encodes digital luminance and colour difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported. The SAA7104E; SAA7105E can be directly connected to a PC video graphics controller with a maximum resolution of 1280 x 1024 (progressive) or 1920 x 1080 (interlaced) at a 50 or 60 Hz frame rate. A programmable scaler scales the computer graphics picture so that it will fit into a standard TV screen with an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Tables 9 to 14. A complete 3 x 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port PD (Pixel Data) or via the I2C-bus. The SAA7104E; SAA7105E supports a 32 x 32 x 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus.
It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. Besides the applications for video output, the SAA7104E; SAA7105E can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port. The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 : 2 : 2 bandwidth in the luminance/colour difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of "RS-170-A" and "ITU-R BT.470-3". For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion. The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figs 4 to 9. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals.
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Philips Semiconductors
Product specification
Digital video encoder
The 8-bit multiplexed CB-Y-CR formats are "ITU-R BT.656" (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of the input data to the rising or falling clock edge see Tables 9 to 14. In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. The SAA7104E; SAA7105E synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus. The IC also contains Closed Caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Fig.14). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). A number of possibilities are provided for setting different video parameters such as: * Black and blanking level control * Colour subcarrier frequency * Variable burst amplitude etc. 7.1 Reset conditions 7.2 CBO Table 2
SAA7104E; SAA7105E
Strapping pins PIN FSVGC TIED LOW PRESET NTSC M encoding, PIXCLK fits to 640 x 480 graphics input
HIGH PAL B/G encoding, PIXCLK fits to 640 x 480 graphics input VSVGC LOW 4 : 2 : 2 Y-CB-CR graphics input (format 0)
HIGH 4 : 4 : 4 RGB graphics input (format 3) LOW input demultiplex phase: LSB = LOW
HIGH input demultiplex phase: LSB = HIGH HSVGC LOW input demultiplex phase: MSB = LOW
HIGH input demultiplex phase: MSB = HIGH TTXRQ_XCLKO2 LOW slave (FSVGC, VSVGC and HSVGC are inputs, internal colour bar is active)
HIGH master (FSVGC, VSVGC and HSVGC are outputs) Input formatter
The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream. When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits SLOT and EDGE for correct operation. If Y-CB-CR is being applied as a 27 Mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block. The horizontal upscaling is supported via the input formatter. According to the programming of the pixel clock dividers (see Section 7.10), it will sample up the data stream to 1 x, 2 x or 4 x the input data rate. An optional interpolation filter is available. The clock domain transition is handled by a 4 entries wide FIFO which gets initialized every field or explicitly at request. A bypass for the FIFO is available, especially for high input data rates.
To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition. After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 2.
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Philips Semiconductors
Product specification
Digital video encoder
7.3 RGB LUT
SAA7104E; SAA7105E
The hot spot is the `tip' of the pointer arrow. It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution. Table 4 BYTE 0 1 2 Cursor bit map D7 D6 D5 D4 D3 D2 D1 D0
The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel. The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. In the latter case, 256 x 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on. 7.4 Cursor insertion
row 0 column 3 row 0 column 7 row 0 column 11 ... row 0 column 27 row 0 column 31 ... row 31 column 27 row 31 column 31
row 0 column 2 row 0 column 6 row 0 column 10 ... row 0 column 26 row 0 column 30 ... row 31 column 26 row 31 column 30
row 0 column 1 row 0 column 5 row 0 column 9 ... row 0 column 25 row 0 column 29 ... row 31 column 25 row 31 column 29
row 0 column 0 row 0 column 4 row 0 column 8 ... row 0 column 24 row 0 column 28 ... row 31 column 24 row 31 column 28
A 32 x 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write access to specific registers or in the pixel data input through the PD port. In the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line. The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the `cursor colours' can be programmed in separate registers. The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner. Table 3 D7 D1 Layout of a byte in the cursor bit map D6 D0 D5 D1 D4 D0 D3 D1 D2 D0 D1 pixel n D1 D0 D0
... 6
7
... 254
255
Table 5
Cursor modes CURSOR MODE CMODE = 0 first cursor colour transparent inverted input CMODE = 1 first cursor colour transparent auxiliary cursor colour
CURSOR PATTERN 00 01 10 11
pixel n + 3
pixel n + 2
pixel n + 1
second cursor colour second cursor colour
For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the `hot spot', the other register controls the insertion position.
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Philips Semiconductors
Product specification
Digital video encoder
7.5 RGB Y-CB-CR matrix
SAA7104E; SAA7105E
The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0. Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in Section 7.20. An additional upscaling mode allows to increase the upscaling factor to maximum 4 as it is required for the old VGA modes like 320 x 240. 7.8 FIFO
RGB input signals to be encoded to PAL or NTSC are converted to the Y-CB-CR colour space in this block. The colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing. A gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235. The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input. When the auxiliary VGA mode is selected, the output of the cursor insertion block is immediately directed to the triple DAC. 7.6 Horizontal scaler
The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically. The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. If the SAA7104E; SAA7105E input data is in accordance with "ITU-R BT.656", the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output. 7.7 Vertical scaler and anti-flicker filter
The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access. In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor. 7.9 Border generator
When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint. 7.10 Oscillator and Discrete Time Oscillator (DTO)
The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler. Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. The circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095 switches it off; see Table 86. An additional, programmable vertical filter supports the anti-flicker function. This filter is not available at upscaling factors of more than 2.
The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exception of the auxiliary VGA or HDTV mode, where the triple DAC is clocked by the pixel clock (PIXCLK). The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 40 and 85 MHz. Two programmable dividers provide the actual clock to be used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8. For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden. 12
2004 Mar 04
Philips Semiconductors
Product specification
Digital video encoder
The internal clock can be switched completely to the pixel clock input. In this event, the input FIFO is useless and will be bypassed. The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock dividers get re-initialized every field. Optionally, the DTO can be cleared with each V-sync. At proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. This is required for some graphic controllers. 7.11 Low-pass Clock Generation Circuit (CGC)
SAA7104E; SAA7105E
The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 4 and 5. The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution. The numeric ratio between the Y and C outputs is in accordance with the standards. 7.12.2 TELETEXT INSERTION AND ENCODING (NOT
SIMULTANEOUSLY WITH REAL-TIME CONTROL)
This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies. 7.12 7.12.1 Encoder VIDEO PATH
Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.14. Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz. 7.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
The encoder generates luminance and colour subcarrier output signals from the Y, CB and CR baseband signals, which are suitable for use as CVBS or separate Y and C signals. Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656 style signal. Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes. Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7104E only. To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 6 and 7. Appropriate transients at start/end of active video and for synchronization pulses are ensured. Chrominance is modified in gain (programmable separately for CB and CR), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be used for the Y and C output. 2004 Mar 04 13
Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16. 7.12.4 CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification of Closed Caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number in which data is to be encoded, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency.
Philips Semiconductors
Product specification
Digital video encoder
Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 7.12.5 ANTI-TAPING (SAA7104E ONLY)
SAA7104E; SAA7105E
If the SAA7104E; SAA7105E is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder. 7.15 HD data path
For more information contact your nearest Philips Semiconductors sales office. 7.13 RGB processor
This data path allows the SAA7104E; SAA7105E to be used with VGA or HDTV monitors. It receives its data directly from the cursor generator and supports RGB and Y-PB-PR output formats (RGB not with Y-PB-PR input formats). No scaling is done in this mode. A gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the signal as it is required for display units expecting signals with sync pulses, either regular or 3-level syncs. 7.16 Timing generator
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 8 and 9. 7.14 Triple DAC
The synchronization of the SAA7104E; SAA7105E is able to operate in two modes; slave mode and master mode. In slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. If the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode. Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0. Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7104E; SAA7105E. In slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the PHRES bits. In the (more common) master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed, they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed.
Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal. The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of the conversion ranges. RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution. The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. Alternatively, all currents can be switched off to reduce power dissipation. All three outputs can be used to sense for an external load (usually 75 ) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. In addition, an automatic sense mode can be activated which indicates a 75 load at any of the three outputs at the dedicated interrupt pin TVD.
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Philips Semiconductors
Product specification
Digital video encoder
The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figs 12 and 13): * The horizontal offset * The length of the active part of the line * The distance from active start to first expected data * The vertical offset separately for odd and even fields * The number of lines per input field. In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7104E; SAA7105E will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 109. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0. 7.17 Pattern generator for HD sync pulses
SAA7104E; SAA7105E
The sequence specifies a series of line types and the number of occurrences of this specific line type. Once the sequence has been completed, it restarts from the beginning. All pulse shapes are filtered internally in order to avoid ringing after analog post filters. The sequence of the generated pulse stream must fit precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame. The sync engines flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. Figure 3 illustrates the context between the various tables. The first table serves as an array to hold the correct sequence of lines that compose the synchronization raster; it can contain up to 16 entries. Each entry holds a 4-bit index to the next table and a 10-bit counter value which specifies how often this particular line is invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. The 4-bit index in the line count array points to the line type array. It holds up to 15 entries (index 0 is not used), index 1 points to the first entry, index 2 to the second entry of the line type array etc. Each entry of the line type array can hold up to 8 index pointers to another table. These indices point to portions of a line pulse pattern: A line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line. Each index of this table points to a particular line of the next table in the linked list. This table is called the line pattern array and each of the up to seven entries stores up to four pairs of a duration in pixel clock cycles and an index to a value table. The table entries are used to define portions of a line representing a certain value for a certain number of clock cycles. The value specified in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into the G or Y signal, only; if bit 4 = 0, the associated value is inserted into all three signals. Two additional bits of the entries in the value array (LSBs of the second byte) determine if the associated events appear as a digital pulse on the HSM_CSYNC and/or VSM outputs.
The pattern generator provides appropriate synchronization patterns for the video data path in auxiliary monitor or HDTV mode. It provides maximum flexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or ATSC formats. The sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values in the outgoing data stream at specified times. It can also be used to generate digital signals associated with time events. These can be used as digital horizontal and vertical synchronization signals on pins HSM_CSYNC and VSM. The picture position is adjustable through the programmable relationship between the sync pulses and the video contents. The generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. Several of these line timing definitions can exist in parallel. For the final sync raster composition a certain sequence of lines with different sync event properties has to be defined.
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Philips Semiconductors
Digital video encoder
4-bit line type index
10-bit line count LINE COUNT ARRAY 16 entries line count pointer
line type pointer
3
3
3
3
3
3
3
3 pattern pointer
LINE TYPE ARRAY 15 entries 3 3 3 3 3 3 3 3
16 16
8 + 2-bit value VALUE ARRAY 8 entries
event type pointer
10-bit duration 4-bit value index
10-bit duration 4-bit value index
10-bit duration 4-bit value index
10-bit duration 4-bit value index
LINE PATTERN ARRAY 7 entries
SAA7104E; SAA7105E
line pattern pointer
MHC573
Product specification
Fig.3 Context between the pattern generator tables for DH sync pulses.
Philips Semiconductors
Product specification
Digital video encoder
To ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster which is defined as width and height. A trigger position can be specified as an x,y co-ordinate within the overall dimensions of the screen raster. If the x,y counter matches the specified co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values. The listing in Table 6 outlines an example on how to set up the sync tables for a 1080i HD raster. Table 6 Example for set-up of the sync tables COMMENT Important note:
SAA7104E; SAA7105E
Due to a problem in the programming interface, writing to the line pattern array (address D2) might destroy the data of the line type array (address D1). A work around is to write the line pattern array data before writing the line type array. Reading of the arrays is possible but all address pointers must be initialized before the next write operation.
SEQUENCE Write to subaddress D0H 00 05 20 01 40 0E 60 1C 12 02 60 01 50 04 20 01 30 0F 60 1C 12 02 60
points to first entry of line count array (index 0) generate 5 lines of line type index 2 (this is the second entry of the line type array); will be the first vertical raster pulse generate 1 line of line type index 4; will be sync-black-sync-black sequence after the first vertical pulse generate 14 lines of line type index 6; will be the following lines with sync-black sequence generate 540 lines of line type index 1; will be lines with sync and active video generate 2 lines of line type index 6; will be the following lines with sync-black sequence generate 1 line of line type index 5; will be the following line (line 563) with sync-black-sync-black-null sequence (null is equivalent to sync tip) generate 4 lines of line type index 2; will be the second vertical raster pulse generate 1 line of line type index 3; will be the following line with sync-null-sync-black sequence generate 15 lines of line type index 6; will be the following lines with sync-black sequence generate 540 lines of line type index 1; will be lines with sync and active video generate 2 lines of line type index 6; will be the following lines with sync-black sequence; now, 1125 lines are defined
Write to subaddress D2H (insertion is done into all three analog output signals) 00 6F 33 2B 30 00 00 00 00 6F 43 2B 30 00 00 00 00 2B 10 2B 20 57 30 00 00 Write to subaddress D1H 00 34 00 00 00 24 24 00 00 24 14 00 00 14 14 00 00 points to first entry of line type array (index 1) use pattern entries 4 and 3 in this sequence (for sync and active video) use pattern entries 4, 2, 4 and 2 in this sequence (for 2 x sync-black-null-black) use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null) use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black) points to first entry of line pattern array (index 1) 880 x value(3) + 44 x value(3); (subtract 1 from real duration) 880 x value(4) + 44 x value(3) 44 x value(1) + 44 x value(2) + 88 x value(3)
3B 30 BF 03 BF 03 2B 30 60 x value(3) + 960 x value(0) + 960 x value(0) + 44 x value(3) 3B 30 BF 33 BF 33 2B 30 60 x value(3) + 960 x value(3) + 960 x value(3) + 44 x value(3)
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
SEQUENCE 14 24 00 00 54 00 00 00
COMMENT use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null) use pattern entries 4 and 5 in this sequence (for sync-black)
Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM) 00 CC 00 80 00 0A 00 CC 00 80 00 Write to subaddress DCH 0B 7.18 I2C-bus interface insertion is active, gain for signal is adapted accordingly Because the analog power-down mode turns off the pixel clock synthesizer, there are limitations in some applications. If there is no pixel clock, the IC is not able to set its outputs to LOW. So, in most cases, DOWNA and DOWND should be set to logic 1 simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down. 7.20 Programming the SAA7104E; SAA7105E points to first entry of value array (index 0) black level, to be added during active video sync level LOW (minimum output voltage) sync level HIGH (3-level sync) black level (needed elsewhere) null (identical to sync level LOW)
The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write and read, except two read only status bytes. The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is assigned to one address. Thus a write access needs the LUT address and three data bytes following subaddress FFH. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address. The I2C-bus slave address is defined as 88H. 7.19 Power-down modes
The SAA7104E; SAA7105E needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream of data from its data source. Because there is no frame memory isolating the data streams, restrictions apply to the input frame timings. Input and output processing of the SAA7104E; SAA7105E are only coupled through the vertical frequencies. In master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing. In slave mode, the encoder receives them. The parameters of the input field are mainly given by the memory capacity of the SAA7104E; SAA7105E. The rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. Therefore, the vertical active video times (and the vertical frequencies) need to be the same. The second rule is that there has to be data in the buffer FIFO when the encoder enters the active video area. Therefore, the vertical offset in the input path needs to be a bit shorter than the offset of the encoder.
In order to reduce the power consumption, the SAA7104E; SAA7105E supports 2 power-down modes, accessible via the I2C-bus. The analog power-down mode (DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. The digital power-down mode turns off all internal clocks and sets the digital outputs to LOW except the I2C-bus interface. The IC keeps its programming and can still be accessed in this mode, however not all registers can be read or written to. Reading or writing to the look-up tables, the cursor and the HD sync generator require a valid pixel clock. The typical supply current in full power-down is approximately 5 mA.
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Philips Semiconductors
Product specification
Digital video encoder
The following Sections give the set of equations required to program the IC for the most common application: A post processor in master mode with non-interlaced video input data. Some variables are defined below: * InPix: the number of active pixels per input line * InPpl: the length of the entire input line in pixel clocks * InLin: the number of active lines per input field/frame * TPclk: the pixel clock period * RiePclk: the ratio of internal to external pixel clock * OutPix: the number of active pixels per output line * OutLin: the number of active lines per output field * TXclk: the encoder clock period (37.037 ns). 7.20.1 TV DISPLAY WINDOW
SAA7104E; SAA7105E
The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function. Thus: 262.5 x 1716 x TXclk TPclk = --------------------------------------------------------------------------------------- (60 Hz) InLin + 2 InPpl x integer --------------------- x 262.5 OutLin 312.5 x 1728 x TXclk TPclk = --------------------------------------------------------------------------------------- (50 Hz) InLin + 2 InPpl x integer --------------------- x 312.5 OutLin and for the pixel clock generator TXclk 20 + PCLE PCL = -------------- x 2 (all frequencies); TPclk see Tables 68, 70 and 71. The divider PCLE should be set according to Table 70. PCLI may be set to a lower or the same value. Setting a lower value means that the internal pixel clock is higher and the data get sampled up. The difference may be 1 at 640 x 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter RiePclk). log RiePclk PCLI = PCLE - ---------------------------- (all frequencies) log 2 The equations ensure that the last line of the field has the full number of clock cycles. Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure that there is not even a fraction of a clock left at the end of the field. 7.20.3 HORIZONTAL SCALER
At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible. The output lines should be centred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 59. ADWHS = 256 + 710 - OutPix (60 Hz); ADWHS = 284 + 702 - OutPix (50 Hz); ADWHE = ADWHS + OutPix x 2 (all frequencies) For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 65. 240 - OutLin FAL = 19 + -------------------------------- (60 Hz); 2 287 - OutLin FAL = 23 + -------------------------------- (50 Hz); 2 LAL = FAL + OutLin (all frequencies) Most TV sets use overscan, and not all pixels respectively lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10%, giving approximately 640 output pixels per line. 7.20.2 INPUT FRAME AND PIXEL CLOCK
XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX HLEN is fulfilled. Values given by the VESA display timings are preferred. HLEN = InPpl x RiePclk - 1 InPix XPIX = ------------ x RiePclk 2 4096 OutPix XINC = ----------------- x ------------------InPix RiePclk XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.
The total number of pixel clocks per line and the input horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses.
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Philips Semiconductors
Product specification
Digital video encoder
7.20.4 VERTICAL SCALER
SAA7104E; SAA7105E
Or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is also limited to less than 1.5. In this case a normal blanking length is sufficient. 7.21 Input levels and formats
The input vertical offset can be taken from the assumption that the scaler should just have finished writing the first line when the encoder starts reading it: FAL x 1716 x TXclk YOFS = --------------------------------------------------- - 2.5 (60 Hz) InPpl x TPclk FAL x 1728 x TXclk YOFS = --------------------------------------------------- - 2.5 (50 Hz) InPpl x TPclk In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down. YPIX = InLin YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. Note that the maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to fulfil this requirement. OutLin YSKIP YINC = --------------------- x 1 + ---------------- x 4096 InLin + 2 4095 YINC YIWGTO = ------------- + 2048 2 YINC - YSKIP YIWGTE = ------------------------------------2 When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive. It should be noted that these equations assume that the input is non-interlaced but the output is interlaced. If the input is interlaced, the initial weighting factors need to be adapted to obtain the proper phase offsets in the output frame. If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may be set to logic 1. This extends the maximum vertical scaling factor by a factor of 2. Only the parameter YINC is affected, it needs to be divided by two to get the same effect. There are restrictions in this mode: * The vertical filter YFILT is not available in this mode; the circuit will ignore this value * The horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. This is 710 internal pixel clocks.
The SAA7104E; SAA7105E accepts digital Y, CB, CR or RGB data with levels (digital codes) in accordance with "ITU-R BT.601". An optional gain adjustment also allows to accept data with the full level swing of 0 to 255. For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The RGB, respectively CR-Y-CB path features an individual gain setting for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. The SAA7104E; SAA7105E has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at 1/2VDDD. To achieve full speed of these cells, the EIDIV bit needs to be set to logic 1. Note that the impedance of these cells is approximately 6 k. This may cause trouble with the bootstrapping pins of some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is regular in this mode. Table 7
"ITU-R BT.601" signal component levels
SIGNALS(1)
COLOUR Y White Yellow Cyan Green Magenta Red Blue Black Note 1. Transformation: a) R = Y + 1.3707 x (CR - 128) b) G = Y - 0.3365 x (CB - 128) - 0.6982 x (CR - 128) c) B = Y + 1.7324 x (CB - 128). 235 210 170 145 106 81 41 16 CB 128 16 166 54 202 90 240 128 CR 128 146 16 34 222 240 110 128 R 235 235 16 16 235 235 16 16 G 235 235 235 235 16 16 16 16 B 235 16 235 16 235 16 235 16
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Philips Semiconductors
Product specification
Digital video encoder
Table 8 Usage of bits SLOT and EDGE DATA SLOT CONTROL (EXAMPLE FOR FORMAT 0) SLOT EDGE 0 0 1 1 0 1 0 1 1st DATA at rising edge G3/Y3 at falling edge G3/Y3 at rising edge R7/CR7 at falling edge R7/CR7 2nd DATA at falling edge R7/CR7 at rising edge R7/CR7 at falling edge G3/Y3 at rising edge G3/Y3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Table 9 Pin assignment for input format 0 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FALLING CLOCK EDGE G3/Y3 G2/Y2 G1/Y1 G0/Y0 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 R2/CR2 R1/CR1 R0/CR0 G7/Y7 G6/Y6 G5/Y5 G4/Y4 PIN PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
SAA7104E; SAA7105E
Table 10 Pin assignment for input format 1 5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB PIN FALLING CLOCK EDGE G2 G1 G0 B4 B3 B2 B1 B0 RISING CLOCK EDGE X R4 R3 R2 R1 R0 G4 G3
Table 11 Pin assignment for input format 2 5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB PIN FALLING CLOCK EDGE G2 G1 G0 B4 B3 B2 B1 B0 RISING CLOCK EDGE R4 R3 R2 R1 R0 G5 G4 G3
Table 12 Pin assignment for input format 3 8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED CB-Y-CR FALLING CLOCK EDGE n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE n Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) FALLING CLOCK EDGE n+1 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE n+1 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
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Philips Semiconductors
Product specification
Digital video encoder
Table 13 Pin assignment for input format 4 8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED CB-Y-CR (ITU-R BT.656, 27 MHz CLOCK) RISING CLOCK EDGE n CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE n+1 Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) RISING CLOCK EDGE n+2 CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE n+3 Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
SAA7104E; SAA7105E
Table 15 Pin assignment for input format 6 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FALLING CLOCK EDGE G4/Y4 G3/Y3 G2/Y2 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 G0/Y0 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 G7/Y7 G6/Y6 G5/Y5 R2/CR2 R1/CR1 R0/CR0 G1/Y1
PIN
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Table 14 Pin assignment for input format 5; note 1 8-BIT NON-INTERLACED INDEX COLOUR PIN PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Note 1. X = don't care. FALLING CLOCK EDGE X X X X INDEX7 INDEX6 INDEX5 INDEX4 INDEX3 INDEX2 INDEX1 INDEX0 RISING CLOCK EDGE X X X X X X X X X X X X
2004 Mar 04
22
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Digital video encoder
Table 16 Slave receiver (slave address 88H) REGISTER FUNCTION Status byte (read only) Null Common DAC adjust fine R DAC adjust coarse G DAC adjust coarse B DAC adjust coarse MSM threshold Monitor sense mode Chip ID (02B or 03B, read only) Wide screen signal Wide screen signal Real-time control, burst start Sync reset enable, burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Input path control Gain luminance for RGB Gain colour difference for RGB Input port control 1 VPS enable, input control 2 VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 Chrominance phase SUB ADDR. (HEX) 00 01 to 15 16 17 18 19 1A 1B 1C 26 27 28 29 2A 2B 2C 2D 2E to 36 37 38 39 3A 54 55 56 57 58 59 5A D7 VER2
(1) (1) (1) (1) (1)
D6 VER1
(1) (1) (1) (1) (1)
D5 VER0
(1) (1) (1) (1) (1)
D4 CCRDO
(1) (1)
D3 CCRDE
(1)
D2
(1) (1)
D1 FSEQ
(1)
D0 O_E
(1)
RDACC4 GDACC4 BDACC4 MSMT4
(1)
DACF3 RDACC3 GDACC3 BDACC3 MSMT3
(1)
DACF2 RDACC2 GDACC2 BDACC2 MSMT2 RCOMP CID2 WSS2 WSS10 BS2 BE2 CG02 CG10 CG18 CLK2EN
(1)
DACF1 RDACC1 GDACC1 BDACC1 MSMT1 GCOMP CID1 WSS1 WSS9 BS1 BE1 CG01 CG09 CG17 CVBSEN2
(1)
DACF0 RDACC0 GDACC0 BDACC0 MSMT0 BCOMP CID0 WSS0 WSS8 BS0 BE0 CG00 CG08 CG16
(1) (1)
MSMT7 MSM CID7 WSS7 WSSON
(1)
MSMT6 MSA CID6 WSS6
(1) (1) (1)
SRES CG07 CG15 CGEN VBSEN
(1) (1) (1) (1)
CG06 CG14
(1)
MSMT5 MSOE CID5 WSS5 WSS13 BS5 BE5 CG05 CG13
(1)
CID4 WSS4 WSS12 BS4 BE4 CG04 CG12
(1)
CVBSEN1
(1)
CVBSEN0
(1)
CEN
(1)
CID3 WSS3 WSS11 BS3 BE3 CG03 CG11 CG19 ENCOFF
(1) (1)
YUPSC
(1) (1) (1) (1)
YFIL1
(1) (1)
YFIL0 GY4 GCD4 SYMP GPEN VPS54 VPS114 VPS124 VPS134 VPS144 CHPS4
GY3 GCD3 DEMOFF
(1)
CZOOM GY2 GCD2 CSYNC
(1)
IGAIN GY1 GCD1 Y2C EDGE VPS51 VPS111 VPS121 VPS131 VPS141 CHPS1
XINT GY0 GCD0 UV2C SLOT VPS50 VPS110 VPS120 VPS130 VPS140 CHPS0
SAA7104E; SAA7105E
CBENB VPSEN VPS57 VPS117 VPS127 VPS137 VPS147 CHPS7
VPS56 VPS116 VPS126 VPS136 VPS146 CHPS6
SYNTV GPVAL VPS55 VPS115 VPS125 VPS135 VPS145 CHPS5
VPS53 VPS113 VPS123 VPS133 VPS143 CHPS3
VPS52 VPS112 VPS122 VPS132 VPS142 CHPS2
Product specification
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Digital video encoder
REGISTER FUNCTION Gain U Gain V Gain U MSB, black level Gain V MSB, blanking level CCR, blanking level VBI Null Standard control Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 Null Trigger control Trigger control Multi control Closed Caption, teletext enable Active display window horizontal start Active display window horizontal end MSBs ADWH TTX request horizontal start TTX request horizontal delay CSYNC advance TTX odd request vertical start TTX odd request vertical end TTX even request vertical start
D7 GAINU7 GAINV7 GAINU8 GAINV8 CCRS1
(1)
D6 GAINU6 GAINV6
(1) (1)
D5 GAINU5 GAINV5 BLCKL5 BLNNL5 BLNVB5
(1)
D4 GAINU4 GAINV4 BLCKL4 BLNNL4 BLNVB4
(1)
D3 GAINU3 GAINV3 BLCKL3 BLNNL3 BLNVB3
(1) (1)
D2 GAINU2 GAINV2 BLCKL2 BLNNL2 BLNVB2
(1)
D1 GAINU1 GAINV1 BLCKL1 BLNNL1 BLNVB1
(1)
D0 GAINU0 GAINV0 BLCKL0 BLNNL0 BLNVB0
(1)
CCRS0
(1)
DOWND RTCE FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17
(1)
DOWNA BSTA6 FSC06 FSC14 FSC22 FSC30 L21O06 L21O16 L21E06 L21E16
(1)
INPI BSTA5 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15
(1)
YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14
(1)
BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13
(1)
SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12
(1)
PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11
(1)
FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10
(1)
HTRIG7 HTRIG10 NVTRIG CCEN1 ADWHS7 ADWHE7
(1)
HTRIG6 HTRIG9 BLCKON CCEN0 ADWHS6 ADWHE6 ADWHE10 TTXHS6
(1)
HTRIG5 HTRIG8 PHRES1 TTXEN ADWHS5 ADWHE5 ADWHE9 TTXHS5
(1)
HTRIG4 VTRIG4 PHRES0 SCCLN4 ADWHS4 ADWHE4 ADWHE8 TTXHS4
(1)
HTRIG3 VTRIG3 LDEL1 SCCLN3 ADWHS3 ADWHE3
(1)
HTRIG2 VTRIG2 LDEL0 SCCLN2 ADWHS2 ADWHE2 ADWHS10 TTXHS2 TTXHD2
(1)
HTRIG1 VTRIG1 FLC1 SCCLN1 ADWHS1 ADWHE1 ADWHS9 TTXHS1 TTXHD1
(1)
HTRIG0 VTRIG0 FLC0 SCCLN0 ADWHS0 ADWHE0 ADWHS8 TTXHS0 TTXHD0
(1)
SAA7104E; SAA7105E
TTXHS7
(1)
CSYNCA4 TTXOVS7 TTXOVE7 TTXEVS7
CSYNCA3 CSYNCA2 CSYNCA1 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVE6 TTXOVE5 TTXOVE4 TTXEVS6 TTXEVS5 TTXEVS4
TTXHS3 TTXHD3 CSYNCA0 TTXOVS3 TTXOVE3 TTXEVS3
Product specification
TTXOVS2 TTXOVE2 TTXEVS2
TTXOVS1 TTXOVE1 TTXEVS1
TTXOVS0 TTXOVE0 TTXEVS0
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Digital video encoder
REGISTER FUNCTION TTX even request vertical end First active line Last active line TTX mode, MSB vertical Null Disable TTX line Disable TTX line FIFO status (read only) Pixel clock 0 Pixel clock 1 Pixel clock 2 Pixel clock control FIFO control Null Horizontal offset Pixel number Vertical offset odd Vertical offset even MSBs Line number Scaler CTRL, MCB YPIX Sync control Line length Input delay, MSB line length Horizontal increment Vertical increment MSBs vertical and horizontal increment Weighting factor odd Weighting factor even Weighting factor MSB Vertical line skip
D7 TTXEVE7 FAL7 LAL7 TTX60
(1)
D6 TTXEVE6 FAL6 LAL6 LAL8
(1)
D5 TTXEVE5 FAL5 LAL5 TTXO
(1)
D4 TTXEVE4 FAL4 LAL4 FAL8
(1)
D3 TTXEVE3 FAL3 LAL3 TTXEVE8
(1)
D2 TTXEVE2 FAL2 LAL2 TTXOVE8
(1)
D1 TTXEVE1 FAL1 LAL1 TTXEVS8
(1)
D0 TTXEVE0 FAL0 LAL0 TTXOVS8
(1)
LINE12 LINE20
(1)
LINE11 LINE19
(1)
LINE10 LINE18
(1)
LINE9 LINE17
(1)
PCL07 PCL15 PCL23 DCLK EIDIV
(1)
PCL06 PCL14 PCL22 PCLSY
(1) (1)
PCL05 PCL13 PCL21 IFRA
(1) (1)
PCL04 PCL12 PCL20 IFBP
(1) (1)
LINE8 LINE16 IFERR PCL03 PCL11 PCL19 PCLE1 FILI3
(1)
LINE7 LINE15 BFERR PCL02 PCL10 PCL18 PCLE0 FILI2
(1)
LINE6 LINE14 OVFL PCL01 PCL09 PCL17 PCLI1 FILI1
(1)
LINE5 LINE13 UDFL PCL00 PCL08 PCL16 PCLI0 FILI0
(1)
XOFS7 XPIX7 YOFSO7 YOFSE7 YOFSE9 YPIX7 EFS HFS HLEN7 IDEL3 XINC7 YINC7 YINC11
XOFS6 XPIX6 YOFSO6 YOFSE6 YOFSE8 YPIX6 PCBN VFS HLEN6 IDEL2 XINC6 YINC6 YINC10
XOFS5 XPIX5 YOFSO5 YOFSE5 YOFSO9 YPIX5 SLAVE OFS HLEN5 IDEL1 XINC5 YINC5 YINC9
XOFS4 XPIX4 YOFSO4 YOFSE4 YOFSO8 YPIX4 ILC PFS HLEN4 IDEL0 XINC4 YINC4 YINC8
XOFS3 XPIX3 YOFSO3 YOFSE3 XPIX9 YPIX3 YFIL OVS HLEN3 HLEN11 XINC3 YINC3 XINC11
XOFS2 XPIX2 YOFSO2 YOFSE2 XPIX8 YPIX2
(1)
PVS HLEN2 HLEN10 XINC2 YINC2 XINC10
XOFS1 XPIX1 YOFSO1 YOFSE1 XOFS9 YPIX1 YPIX9 OHS HLEN1 HLEN9 XINC1 YINC1 XINC9
XOFS0 XPIX0 YOFSO0 YOFSE0 XOFS8 YPIX0 YPIX8 PHS HLEN0 HLEN8 XINC0 YINC0 XINC8 YIWGTO0 YIWGTE0 YIWGTO8 YSKIP0
SAA7104E; SAA7105E
Product specification
YIWGTO7 YIWGTO6 YIWGTO5 YIWGTE7 YIWGTE6 YIWGTE5 YIWGTE11 YIWGTE10 YIWGTE9 YSKIP7 YSKIP6 YSKIP5
YIWGTO4 YIWGTO3 YIWGTO2 YIWGTO1 YIWGTE4 YIWGTE3 YIWGTE2 YIWGTE1 YIWGTE8 YIWGTO11 YIWGTO10 YIWGTO9 YSKIP4 YSKIP3 YSKIP2 YSKIP1
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Digital video encoder
REGISTER FUNCTION Blank enable for NI-bypass, vertical line skip MSB Border colour Y Border colour U Border colour V HD sync line count array HD sync line type array HD sync line pattern array HD sync value array HD sync trigger state 1 HD sync trigger state 2 HD sync trigger state 3 HD sync trigger state 4 HD sync trigger phase x
D7 BLEN BCY7 BCU7 BCV7
D6
(1)
D5
(1)
D4
(1)
D3 YSKIP11
D2 YSKIP10 BCY2 BCU2 BCV2
D1 YSKIP9 BCY1 BCU1 BCV1
D0 YSKIP8 BCY0 BCU0 BCV0
BCY6 BCU6 BCV6
BCY5 BCU5 BCV5
BCY4 BCY3 BCU4 BCU3 BCV4 BCV3 RAM address (see Table 89) RAM address (see Table 91) RAM address (see Table 93) RAM address (see Table 95) HLCT4 HLCPT0 HDCT4 HEPT0 HTX4
(1)
HLCT7 HLCPT3 HDCT7
(1)
HLCT6 HLCPT2 HDCT6 HEPT2 HTX6
(1)
HLCT5 HLCPT1 HDCT5 HEPT1 HTX5
(1)
HLCT3 HLPPT1 HDCT3
(1)
HLCT2 HLPPT0 HDCT2
(1)
HLCT1 HLCT9 HDCT1 HDCT9 HTX1 HTX9 HTY1 HTY9 HDGY CC1R1 CC1G1 CC1B1 CC2R1 CC2G1 CC2B1 AUXR1 AUXG1 AUXB1 XCP1 XCP9 YCP1 YCP9
HLCT0 HLCT8 HDCT0 HDCT8 HTX0 HTX8 HTY0 HTY8 HDIP CC1R0 CC1G0 CC1B0 CC2R0 CC2G0 CC2B0 AUXR0 AUXG0 AUXB0 XCP0 XCP8 YCP0 YCP8
HTX7
(1)
HTY7
(1) (1)
HTY6
(1) (1)
HTY5
(1) (1)
HTY4
(1) (1)
HTX3 HTX11 HTY3
(1)
HTX2 HTX10 HTY2
(1)
CC1R7 CC1G7 CC1B7 CC2R7 CC2G7 CC2B7 AUXR7 AUXG7 AUXB7 XCP7 XHS4 YCP7 YHS4
CC1R6 CC1G6 CC1B6 CC2R6 CC2G6 CC2B6 AUXR6 AUXG6 AUXB6 XCP6 XHS3 YCP6 YHS3
CC1R5 CC1G5 CC1B5 CC2R5 CC2G5 CC2B5 AUXR5 AUXG5 AUXB5 XCP5 XHS2 YCP5 YHS2
CC1R4 CC1G4 CC1B4 CC2R4 CC2G4 CC2B4 AUXR4 AUXG4 AUXB4 XCP4 XHS1 YCP4 YHS1
HDSYE CC1R3 CC1G3 CC1B3 CC2R3 CC2G3 CC2B3 AUXR3 AUXG3 AUXB3 XCP3 XHS0 YCP3 YHS0
HDTC CC1R2 CC1G2 CC1B2 CC2R2 CC2G2 CC2B2 AUXR2 AUXG2 AUXB2 XCP2 XCP10 YCP2
(1)
SAA7104E; SAA7105E
Product specification
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Digital video encoder
REGISTER FUNCTION Input path control Cursor bit map Colour look-up table Note
D7 LUTOFF
D6 CMODE
D5 LUTL
D4 IF2
D3 IF1
D2 IF0
D1 MATOFF
D0 DFOFF
RAM address (see Table 110) RAM address (see Table 111)
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
SAA7104E; SAA7105E
Product specification
Philips Semiconductors
Product specification
Digital video encoder
7.23 I2C-bus format
SAA7104E; SAA7105E
Table 17 I2C-bus write access to control registers; see Table 23 S 10001000 A SUBADDRESS A DATA 0 A -------DATA n A P
Table 18 I2C-bus write access to the HD line count array (subaddress D0H); see Table 23 S 10001000 A D0H A RAM ADDRESS A DATA 00 A DATA 01 A -------DATA n A P
Table 19 I2C-bus write access to cursor bit map (subaddress FEH); see Table 23 S 10001000 A FEH A RAM ADDRESS A DATA 0 A -------DATA n A P
Table 20 I2C-bus write access to colour look-up table (subaddress FFH); see Table 23 S 10001000 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A -------P
Table 21 I2C-bus read access to control registers; see Table 23 S 10001000 A SUBADDRESS A Sr 10001001 A DATA 0 Am -------DATA n Am P
Table 22 I2C-bus read access to cursor bit map or colour LUT; see Table 23 S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P or FFH Table 23 Explanations of Tables 17 to 22 CODE S Sr 1 0 0 0 1 0 0 X; note 1 A Am SUBADDRESS; note 2 DATA -------P RAM ADDRESS Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. 2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. START condition repeated START condition slave address acknowledge generated by the slave acknowledge generated by the master subaddress byte data byte continued data bytes and acknowledges STOP condition start address for RAM access DESCRIPTION
2004 Mar 04
28
Philips Semiconductors
Product specification
Digital video encoder
7.24 Slave receiver
SAA7104E; SAA7105E
Table 24 Subaddress 16H DATA BYTE DACF DESCRIPTION output level adjustment fine in 1% steps for all DACs; default after reset is 00H; see Table 25
Table 25 Fine adjustment of DAC output voltage BINARY 0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 Table 26 Subaddresses 17H to 19H DATA BYTE RDACC GDACC BDACC DESCRIPTION output level coarse adjustment for RED DAC; default after reset is 1BH for output of C signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion output level coarse adjustment for GREEN DAC; default after reset is 1BH for output of VBS signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion output level coarse adjustment for BLUE DAC; default after reset is 1FH for output of CVBS signal 00000b 0.585 V to 11111b 1.240 V at 37.5 nominal for full-scale conversion GAIN (%) 7 6 5 4 3 2 1 0 0 -1 -2 -3 -4 -5 -6 -7
Table 27 Subaddress 1AH DATA BYTE MSMT DESCRIPTION monitor sense mode threshold for DAC output voltage, should be set to 70
2004 Mar 04
29
Philips Semiconductors
Product specification
Digital video encoder
Table 28 Subaddress 1BH DATA BYTE MSM MSA LOGIC LEVEL 0 1 0 1 MSOE RCOMP (read only) GCOMP (read only) BCOMP (read only) 0 1 0 1 0 1 0 1 monitor sense mode on DESCRIPTION
SAA7104E; SAA7105E
monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset automatic monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset automatic monitor sense mode on if MSM = 0 pin TVD is active pin TVD is 3-state; default after reset check comparator at DAC on pin RED_CR_C_CVBS is active, output is loaded check comparator at DAC on pin RED_CR_C_CVBS is inactive, output is not loaded check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
Table 29 Subaddresses 26H and 27H DATA BYTE WSS LOGIC LEVEL - wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON 0 1 wide screen signalling output is disabled; default after reset wide screen signalling output is enabled DESCRIPTION
Table 30 Subaddress 28H DATA BYTE BS LOGIC LEVEL - DESCRIPTION starting point of burst in clock cycles REMARKS PAL: BS = 33 (21H); default after reset if strapping pin FSVGC tied to HIGH NTSC: BS = 25 (19H); default after reset if strapping pin FSVGC tied to LOW
2004 Mar 04
30
Philips Semiconductors
Product specification
Digital video encoder
Table 31 Subaddress 29H DATA BYTE SRES LOGIC LEVEL 0 1 BE - DESCRIPTION pin TTX_SRES accepts a teletext bit stream (TTX) pin TTX_SRES accepts a sync reset input (SRES) ending point of burst in clock cycles
SAA7104E; SAA7105E
REMARKS default after reset a HIGH impulse resets synchronization of the encoder (first field, first line) PAL: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to HIGH NTSC: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to LOW
Table 32 Subaddresses 2AH to 2CH DATA BYTE CG LOGIC LEVEL - DESCRIPTION LSBs of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format. copy generation data output is disabled; default after reset copy generation data output is enabled
CGEN
0 1
Table 33 Subaddress 2DH DATA BYTE VBSEN LOGIC LEVEL 0 1 CVBSEN1 0 1 CVBSEN0 CEN 0 1 0 1 ENCOFF CLK2EN 0 1 0 1 CVBSEN2 0 1 DESCRIPTION pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS signal (CVBSEN1 = 1) pin GREEN_VBS_CVBS provides a luminance (VBS) signal; default after reset pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal; default after reset pin GREEN_VBS_CVBS provides a CVBS signal pin BLUE_CB_CVBS provides a component BLUE (B) or colour difference BLUE (CB) signal pin BLUE_CB_CVBS provides a CVBS signal; default after reset pin RED_CR_C_CVBS provides a component RED (R) or colour difference RED (CR) signal pin RED_CR_C_CVBS provides a chrominance signal (C) as modulated subcarrier for S-video; default after reset encoder is active; default after reset encoder bypass, DACs are provided with RGB signal after cursor insertion block pin TTXRQ_XCLKO2 provides a teletext request signal (TTXRQ) pin TTXRQ_XCLKO2 provides the buffered crystal clock divided by two (13.5 MHz); default after reset pin RED_CR_C_CVBS provides a signal according to CEN; default after reset pin RED_CR_C_CVBS provides a CVBS signal
2004 Mar 04
31
Philips Semiconductors
Product specification
Digital video encoder
Table 34 Subaddress 37H DATA BYTE YUPSC YFIL CZOOM IGAIN XINT LOGIC LEVEL 0 1 - 0 1 0 1 0 1 vertical upscaling is enabled
SAA7104E; SAA7105E
DESCRIPTION normal operation of the vertical scaler; default after reset controls the vertical interpolation filter, see Table 35; the filter is not available if YUPSC = 1 normal operation of the cursor generator; default after reset the cursor will be zoomed by a factor of 2 in both directions expected input level swing is 16 to 235 (8-bit RGB); default after reset expected input level swing is 0 to 255 (8-bit RGB) no horizontal interpolation filter; default after reset interpolation filter for horizontal upscaling is active
Table 35 Logic levels and function of YFIL DATA BYTE DESCRIPTION YFIL1 0 0 1 1 YFIL0 0 1 0 1 no filter active; default after reset filter is inserted before vertical scaling filter is inserted after vertical scaling; YSKIP should be logic 0 reserved
Table 36 Subaddresses 38H and 39H DATA BYTE GY4 to GY0 GCD4 to GCD0 DESCRIPTION Gain luminance of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application. Gain colour difference of RGB (CR, Y and CB) output, ranging from (1 - 1632) to (1 + 1532). Suggested nominal value = 0, depending on external application.
2004 Mar 04
32
Philips Semiconductors
Product specification
Digital video encoder
Table 37 Subaddress 3AH DATA BYTE CBENB SYNTV LOGIC LEVEL 0 1 0 1 SYMP 0 1 DEMOFF CSYNC 0 1 0 1 Y2C UV2C 0 1 0 1 Table 38 Subaddress 54H DATA BYTE VPSEN GPVAL GPEN EDGE SLOT LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 DESCRIPTION data from input ports is encoded colour bar with fixed colours is encoded DESCRIPTION
SAA7104E; SAA7105E
in slave mode, the encoder is only synchronized at the beginning of an odd field; default after reset in slave mode, the encoder receives a vertical sync signal horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default after reset horizontal and vertical trigger is decoded out of "ITU-R BT.656" compatible data at PD port Y-CB-CR to RGB dematrix is active; default after reset Y-CB-CR to RGB dematrix is bypassed pin HSM_CSYNC provides a horizontal sync for non-interlaced VGA components output (at PIXCLK) pin HSM_CSYNC provides a composite sync for interlaced components output (at XTAL clock) input luminance data is twos complement from PD input port input luminance data is straight binary from PD input port; default after reset input colour difference data is twos complement from PD input port input colour difference data is straight binary from PD input port; default after reset
video programming system data insertion is disabled; default after reset video programming system data insertion in line 16 is enabled pin VSM provides a LOW level if GPEN = 1 pin VSM provides a HIGH level if GPEN = 1 pin VSM provides a vertical sync for a monitor; default after reset pin VSM provides a constant signal according to GPVAL input data is sampled with inverse clock edges input data is sampled with the clock edges specified in Tables 9 to 14; default after reset normal assignment of the input data to the clock edge; default after reset correct time misalignment due to inverted assignment of input data to the clock edge
Table 39 Subaddresses 55H to 59H DATA BYTE VPS5 VPS11 VPS12 VPS13 VPS14 2004 Mar 04 DESCRIPTION fifth byte of video programming system data eleventh byte of video programming system data twelfth byte of video programming system data thirteenth byte of video programming system data fourteenth byte of video programming system data 33 REMARKS in line 16; LSB first; all other bytes are not relevant for VPS
Philips Semiconductors
Product specification
Digital video encoder
Table 40 Subaddress 5AH; note 1 DATA BYTE CHPS DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees VALUE 6BH 16H 25H 46H Note 1. The default after reset is 00H. Table 41 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for CB signal; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-black = 92.5 IRE GAINU = 0 GAINU = 118 (76H) white-to-black = 100 IRE GAINU = 0 GAINU = 125 (7DH) Table 42 Subaddresses 5CH and 5EH DATA BYTE GAINV DESCRIPTION variable gain for CR signal; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-black = 92.5 IRE GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 IRE GAINV = 0 GAINV = 175 (AFH) Table 43 Subaddress 5DH DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with "ITU-R BT.601" CONDITIONS white-to-sync = 140 IRE; note 1 BLCKL = 0; note 1 white-to-sync = 143 IRE; note 2 BLCKL = 0; note 2
SAA7104E; SAA7105E
RESULT PAL B/G and data from input ports in master mode PAL B/G and data from look-up table NTSC M and data from input ports in master mode NTSC M and data from look-up table
REMARKS GAINU = -2.17 x nominal to +2.16 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = -2.05 x nominal to +2.04 x nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal
REMARKS GAINV = -1.55 x nominal to +1.55 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal GAINV = -1.46 x nominal to +1.46 x nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal
REMARKS recommended value: BLCKL = 58 (3AH) output black level = 29 IRE recommended value: BLCKL = 51 (33H) output black level = 27 IRE
BLCKL = 63 (3FH); note 1 output black level = 49 IRE
BLCKL = 63 (3FH); note 2 output black level = 47 IRE Notes 1. Output black level/IRE = BLCKL x 2/6.29 + 28.9. 2. Output black level/IRE = BLCKL x 2/6.18 + 26.5.
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Philips Semiconductors
Product specification
Digital video encoder
Table 44 Subaddress 5EH DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE; note 1 BLNNL = 0; note 1 BLNNL = 63 (3FH); note 1 white-to-sync = 143 IRE; note 2 BLNNL = 0; note 2 BLNNL = 63 (3FH); note 2 Notes 1. Output black level/IRE = BLNNL x 2/6.29 + 25.4. 2. Output black level/IRE = BLNNL x 2/6.18 + 25.9; default after reset: 35H. Table 45 Subaddress 5FH DATA BYTE CCRS BLNVB DESCRIPTION select cross-colour reduction filter in luminance; see Table 46
SAA7104E; SAA7105E
REMARKS recommended value: BLNNL = 46 (2EH) output blanking level = 25 IRE output blanking level = 45 IRE recommended value: BLNNL = 53 (35H) output blanking level = 26 IRE output blanking level = 46 IRE
variable blanking level during vertical blanking interval is typically identical to value of BLNNL
Table 46 Logic levels and function of CCRS CCRS1 0 0 1 1 CCRS0 0 1 0 1 DESCRIPTION no cross-colour reduction; for overall transfer characteristic of luminance see Fig.6 cross-colour reduction #1 active; for overall transfer characteristic see Fig.6 cross-colour reduction #2 active; for overall transfer characteristic see Fig.6 cross-colour reduction #3 active; for overall transfer characteristic see Fig.6
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
Table 47 Subaddress 61H DATA BYTE DOWND DOWNA INPI YGS SCBW LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 PAL FISE 0 1 0 1 DESCRIPTION
SAA7104E; SAA7105E
digital core in normal operational mode; default after reset digital core in sleep mode and is reactivated with an I2C-bus address DACs in normal operational mode; default after reset DACs in power-down mode PAL switch phase is nominal; default after reset PAL switch is inverted compared to nominal if RTCE = 1 luminance gain for white - black 100 IRE luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 4 and 5) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 4 and 5); default after reset NTSC encoding (non-alternating V component) PAL encoding (alternating V component) 864 total pixel clocks per line 858 total pixel clocks per line
Table 48 Subaddress 62H DATA BYTE RTCE LOGIC LEVEL 0 1 DESCRIPTION CONDITIONS REMARKS
no real-time control of generated subcarrier frequency; default after reset real-time control of generated subcarrier frequency through a Philips video decoder; for a specification of the RTC protocol see document "RTC Functional Description", available on request amplitude of colour burst; input representation in accordance with "ITU-R BT.601" white-to-black = 92.5 IRE; recommended value: burst = 40 IRE; NTSC encoding BSTA = 63 (3FH) BSTA = 0 to 2.02 x nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 2.82 x nominal white-to-black = 100 IRE; recommended value: burst = 43 IRE; NTSC encoding BSTA = 67 (43H) BSTA = 0 to 1.90 x nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 x nominal recommended value: BSTA = 47 (2FH); default after reset recommended value: BSTA = 45 (2DH)
BSTA
-
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
Table 49 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS REMARKS
FSC0 to FSC3 ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) Note 1. Examples:
FSC3 = most significant byte; f fsc 32 FSC = round ------- x 2 ; FSC0 = least significant byte f llc note 1
a) NTSC M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH). Table 50 Subaddresses 67H to 6AH DATA BYTE L21O0 L21O1 L21E0 L21E1 DESCRIPTION first byte of captioning data, odd field REMARKS
LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective second byte of captioning data, odd field bytes have to carry the parity bit, in accordance with the first byte of extended data, even field definition of line 21 encoding format. second byte of extended data, even field
Table 51 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to chip-internal horizontal input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; the default value is 0 Table 52 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to chip-internal vertical input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH); the default value is 0 Table 53 Subaddress 6EH DATA BYTE NVTRIG BLCKON PHRES LDEL FLC LOGIC LEVEL 0 1 0 1 - - - DESCRIPTION values of the VTRIG register are positive values of the VTRIG register are negative encoder in normal operation mode; default after reset output signal is forced to blanking level selects the phase reset mode of the colour subcarrier generator; see Table 54 selects the delay on luminance path with reference to chrominance path; see Table 55 field length control; see Table 56
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Philips Semiconductors
Product specification
Digital video encoder
Table 54 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 0 0 1 1 PHRES0 0 1 0 1 no subcarrier reset subcarrier reset every two lines subcarrier reset every eight fields subcarrier reset every four fields
SAA7104E; SAA7105E
Table 55 Logic levels and function of LDEL DATA BYTE DESCRIPTION LDEL1 0 0 1 1 LDEL0 0 1 0 1 no luminance delay; default after reset 1 LLC luminance delay 2 LLC luminance delay 3 LLC luminance delay
Table 56 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 0 0 1 1 FLC0 0 1 0 1 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 57 Subaddress 6FH DATA BYTE CCEN TTXEN SCCLN LOGIC LEVEL - 0 1 - DESCRIPTION enables individual line 21 encoding; see Table 58 disables teletext insertion; default after reset enables teletext insertion selects the actual line, where Closed Caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
Table 58 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 line 21 encoding off; default after reset enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
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Philips Semiconductors
Product specification
Digital video encoder
Table 59 Subaddresses 70H to 72H DATA BYTE ADWHS DESCRIPTION
SAA7104E; SAA7105E
active display window horizontal start; defines the start of the active TV display portion after the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed active display window horizontal end; defines the end of the active TV display portion before the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
ADWHE
Table 60 Subaddress 73H DATA BYTE TTXHS DESCRIPTION start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0); see Fig.14 REMARKS TTXHS = 42H; is default after reset if strapped to PAL TTXHS = 54H; is default after reset if strapped to NTSC Table 61 Subaddress 74H DATA BYTE TTXHD DESCRIPTION REMARKS
indicates the delay in clock cycles between rising edge of TTXRQ minimum value: TTXHD = 2; output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at is default after reset pin TTX_SRES
Table 62 Subaddress 75H DATA BYTE CSYNCA DESCRIPTION advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks
Table 63 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems REMARKS TTXOVS = 05H; is default after reset if strapped to PAL TTXOVS = 06H; is default after reset if strapped to NTSC TTXOVE = 16H; is default after reset if strapped to PAL TTXOVE = 10H; is default after reset if strapped to NTSC
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Philips Semiconductors
Product specification
Digital video encoder
Table 64 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems Table 65 Subaddresses 7AH to 7CH DATA BYTE FAL LAL DESCRIPTION
SAA7104E; SAA7105E
REMARKS TTXEVS = 04H; is default after reset if strapped to PAL TTXEVS = 05H; is default after reset if strapped to NTSC TTXEVE = 16H; is default after reset if strapped to PAL TTXEVE = 10H; is default after reset if strapped to NTSC
first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M-systems and LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse
Table 66 Subaddress 7CH DATA BYTE TTX60 TTXO LOGIC LEVEL 0 1 0 1 DESCRIPTION enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset enables world standard teletext 60 Hz (FISE = 1) new teletext protocol selected; at each rising edge of TTXRQ a single teletext bit is requested (see Fig.14); default after reset old teletext protocol selected; the encoder provides a window of TTXRQ going HIGH; the length of the window depends on the chosen teletext standard (see Fig.14)
Table 67 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE Table 68 Subaddresses 81H to 83H DATA BYTE PCL DESCRIPTION defines the frequency of the synthesized pixel clock PIXCLKO; PCL f PIXCLK = ---------- x f XTAL x 8 ; fXTAL = 27 MHz nominal, e.g. 640 x 480 to NTSC M: PCL = 20F63BH; 24 2 640 x 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
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Philips Semiconductors
Product specification
Digital video encoder
Table 69 Subaddress 84H DATA BYTE DCLK PCLSY IFRA IFBP PCLE PCLI LOGIC LEVEL - 0 1 0 1 0 1 - -
SAA7104E; SAA7105E
DESCRIPTION set to logic 1 (default after reset is logic 0) pixel clock generator runs free; default after reset pixel clock generator gets synchronized with the vertical sync input FIFO gets reset explicitly at falling edge input FIFO gets reset every field; default after reset input FIFO is active input FIFO is bypassed; default after reset controls the divider for the external pixel clock; see Table 70 controls the divider for the internal pixel clock; see Table 71
Table 70 Logic levels and function of PCLE DATA BYTE DESCRIPTION PCLE1 0 0 1 1 PCLE0 0 1 0 1 divider ratio for PIXCLK output is 1 divider ratio for PIXCLK output is 2; default after reset divider ratio for PIXCLK output is 4 divider ratio for PIXCLK output is 8
Table 71 Logic levels and function of PCLI DATA BYTE DESCRIPTION PCLI1 0 0 1 1 PCLI0 0 1 0 1 divider ratio for internal PIXCLK is 1 divider ratio for internal PIXCLK is 2; default after reset divider ratio for internal PIXCLK is 4 not allowed
Table 72 Subaddress 85H DATA BYTE EIDIV FILI LOGIC LEVEL 0 1 - DESCRIPTION set to logic 0 if DVO compliant signals are applied; default after reset set to logic 1 if non-DVO compliant signals are applied threshold for FIFO internal transfers; nominal value is 8; default after reset
Table 73 Subaddresses 90H and 94H DATA BYTE XOFS DESCRIPTION horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output
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Philips Semiconductors
Product specification
Digital video encoder
Table 74 Subaddresses 91H and 94H DATA BYTE XPIX DESCRIPTION
SAA7104E; SAA7105E
pixel in X direction; defines half the number of active pixels per input line (identical to the length of CBO pulses)
Table 75 Subaddresses 92H and 94H DATA BYTE YOFSO DESCRIPTION vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
Table 76 Subaddresses 93H and 94H DATA BYTE YOFSE DESCRIPTION vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
Table 77 Subaddresses 95H and 96H DATA BYTE YPIX DESCRIPTION defines the number of requested input lines from the feeding device; number of requested lines = YPIX + YOFSE - YOFSO
Table 78 Subaddress 96H DATA BYTE EFS PCBN SLAVE ILC YFIL LOGIC LEVEL 0 1 0 1 0 1 0 1 0 1 DESCRIPTION frame sync signal at pin FSVGC ignored in slave mode frame sync signal at pin FSVGC accepted in slave mode normal polarity of CBO signal (HIGH during active video) inverted polarity of CBO signal (LOW during active video) the SAA7104E; SAA7105E is timing master to the graphics controller the SAA7104E; SAA7105E is timing slave to the graphics controller if hardware cursor insertion is active, set LOW for non-interlaced input signals if hardware cursor insertion is active, set HIGH for interlaced input signals luminance sharpness booster disabled luminance sharpness booster enabled
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Philips Semiconductors
Product specification
Digital video encoder
Table 79 Subaddress 97H DATA BYTE HFS LOGIC LEVEL 0 1 VFS 0 1 OFS PFS 0 1 0 1 OVS PVS 0 1 0 1 OHS PHS 0 1 0 1
SAA7104E; SAA7105E
DESCRIPTION horizontal sync is directly derived from input signal (slave mode) at pin HSVGC horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) vertical sync (field sync) is directly derived from input signal (slave mode) at pin VSVGC vertical sync (field sync) is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) pin FSVGC is switched to input pin FSVGC is switched to active output polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode pin VSVGC is switched to input pin VSVGC is switched to active output polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode pin HSVGC is switched to input pin HSVGC is switched to active output polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode
Table 80 Subaddresses 98H and 99H DATA BYTE HLEN DESCRIPTION number of PIXCLKs horizontal length; HLEN = ---------------------------------------------------- - 1 line
Table 81 Subaddress 99H DATA BYTE IDEL DESCRIPTION input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel
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Philips Semiconductors
Product specification
Digital video encoder
Table 82 Subaddresses 9AH and 9CH DATA BYTE XINC DESCRIPTION
SAA7104E; SAA7105E
number of output pixels ------------------------------------------------------------line incremental fraction of the horizontal scaling engine; XINC = ------------------------------------------------------------- x 4096 number of input pixels --------------------------------------------------------line
Table 83 Subaddresses 9BH and 9CH DATA BYTE YINC DESCRIPTION number of active output lines incremental fraction of the vertical scaling engine; YINC = --------------------------------------------------------------------------- x 4096 number of active input lines
Table 84 Subaddresses 9DH and 9FH DATA BYTE YIWGTO DESCRIPTION YINC weighting factor for the first line of the odd field; YIWGTO = ------------- + 2048 2
Table 85 Subaddresses 9EH and 9FH DATA BYTE YIWGTE DESCRIPTION YINC - YSKIP weighting factor for the first line of the even field; YIWGTE = ------------------------------------2
Table 86 Subaddresses A0H and A1H DATA BYTE YSKIP DESCRIPTION vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective; YSKIP = 4095: anti-flicker filter switched off
Table 87 Subaddress A1H DATA BYTE BLEN LOGIC LEVEL 0 1 DESCRIPTION no internal blanking for non-interlaced graphics in bypass mode; default after reset forced internal blanking for non-interlaced graphics in bypass mode
Table 88 Subaddresses A2H to A4H DATA BYTE BCY, BCU and BCV DESCRIPTION luminance and colour difference portion of border colour in underscan area
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Philips Semiconductors
Product specification
Digital video encoder
Table 89 Subaddress D0H DATA BYTE HLCA DESCRIPTION
SAA7104E; SAA7105E
RAM start address for the HD sync line count array; the byte following subaddress D0 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line count array entry consists of 2 bytes; see Table 90. The array has 15 entries. HD line counter. The system will repeat the pattern described in `HLT' HLC times and then start with the next entry in line count array. HD line type pointer. If not 0, the value points into the line type array, index HLT - 1 with the description of the current line. 0 means the entry is not used.
HLC HLT
Table 90 Layout of the data bytes in the line count array BYTE 0 1 HLC7 HLT3 HLC6 HLT2 HLC5 HLT1 DESCRIPTION HLC4 HLT0 HLC3 0 HLC2 0 HLC1 HLC9 HLC0 HLC8
Table 91 Subaddress D1H DATA BYTE HLTA DESCRIPTION RAM start address for the HD sync line type array; the byte following subaddress D1 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line type array entry consists of 4 bytes; see Table 92. The array has 15 entries. HD line type; if not 0, the value points into the line pattern array. The index used is HLP - 1. It consists of value-duration pairs. Each entry consists of 8 pointers, used from index 0 to 7. The value 0 means that the entry is not used.
HLP
Table 92 Layout of the data bytes in the line type array BYTE 0 1 2 3 0 0 0 0 HLP12 HLP32 HLP52 HLP72 HLP11 HLP31 HLP51 HLP71 DESCRIPTION HLP10 HLP30 HLP50 HLP70 0 0 0 0 HLP02 HLP22 HLP42 HLP62 HLP01 HLP21 HLP41 HLP61 HLP00 HLP20 HLP40 HLP60
Table 93 Subaddress D2H DATA BYTE HLPA DESCRIPTION RAM start address for the HD sync line pattern array; the byte following subaddress D2 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line pattern array entry consists of 4 value-duration pairs occupying 2 bytes; see Table 94. The array has 7 entries. HD pattern duration. The value defines the time in pixel clocks (HPD + 1) the corresponding value HPV is added to the HD output signal. If 0, this entry will be skipped. HD pattern value pointer. This gives the index in the HD value array containing the level to be inserted into the HD output path. If the MSB of HPV is logic 1, the value will only be inserted into the Y/GREEN channel of the HD data path, the other channels remain unchanged.
HPD HPV
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Philips Semiconductors
Product specification
Digital video encoder
Table 94 Layout of the data bytes in the line pattern array BYTE 0 1 2 3 4 5 6 7 HPD07 HPV03 HPD17 HPV13 HPD27 HPV23 HPD37 HPV33 HPD06 HPV02 HPD16 HPV12 HPD26 HPV22 HPD36 HPV32 HPD05 HPV01 HPD14 HPV11 HPD25 HPV21 HPD35 HPV31 DESCRIPTION HPD04 HPV00 HPD14 HPV10 HPD24 HPV20 HPD34 HPV30 HPD03 0 HPD13 0 HPD23 0 HPD33 0
SAA7104E; SAA7105E
HPD02 0 HPD12 0 HPD22 0 HPD32 0
HPD01 HPD09 HPD11 HPD19 HPD21 HPD29 HPD31 HPD39
HPD00 HPD08 HPD10 HPD18 HPD20 HPD28 HPD30 HPD38
Table 95 Subaddress D3H DATA BYTE HPVA DESCRIPTION RAM start address for the HD sync value array; the byte following subaddress D3 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line pattern array entry consists of 2 bytes. The array has 8 entries. HD pattern value entry. The HD path will insert a level of (HPV + 52) x 0.66 IRE into the data path. The value is signed 8-bits wide; see Table 96. HD horizontal sync. If the HD engine is active, this value will be provided at pin HSM_CSYNC; see Table 96. HD vertical sync. If the HD engine is active, this value will be provided at pin VSM; see Table 96.
HPVE HHS HVS
Table 96 Layout of the data bytes in the value array BYTE 0 1 HPVE7 0 HPVE6 0 HPVE5 0 DESCRIPTION HPVE4 0 HPVE3 0 HPVE2 0 HPVE1 HVS HPVE0 HHS
Table 97 Subaddresses D4H and D5H DATA BYTE HLCT HLCPT HLPPT DESCRIPTION state of the HD line counter after trigger, note that it counts backwards state of the HD line type pointer after trigger state of the HD pattern pointer after trigger
Table 98 Subaddresses D6H and D7H DATA BYTE HDCT HEPT DESCRIPTION state of the HD duration counter after trigger, note that it counts backwards state of the HD event type pointer in the line type array after trigger
Table 99 Subaddresses D8H and D9H DATA BYTE HTX DESCRIPTION horizontal trigger phase for the HD sync engine in pixel clocks
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Philips Semiconductors
Product specification
Digital video encoder
Table 100 Subaddresses DAH and DBH DATA BYTE HTY DESCRIPTION vertical trigger phase for the HD sync engine in input lines
SAA7104E; SAA7105E
Table 101 Subaddress DCH DATA BYTE HDSYE HDTC HDGY LOGIC LEVEL 0 1 0 1 0 1 HDIP 0 1 the HD sync engine is active HD output path processes RGB; default after reset HD output path processes YUV gain in the HD output path is reduced, insertion of sync pulses is possible; default after reset full level swing at the input causes full level swing at the DACs in HD mode interpolator for the colour difference signal in the HD output path is active; default after reset interpolator for the colour difference signals in the HD output path is off DESCRIPTION the HD sync engine is off; default after reset
Table 102 Subaddresses F0H to F2H DATA BYTE CC1R, CC1G and CC1B DESCRIPTION RED, GREEN and BLUE portion of first cursor colour
Table 103 Subaddresses F3H to F5H DATA BYTE CC2R, CC2G and CC2B DESCRIPTION RED, GREEN and BLUE portion of second cursor colour
Table 104 Subaddresses F6H to F8H DATA BYTE AUXR, AUXG and AUXB DESCRIPTION RED, GREEN and BLUE portion of auxiliary cursor colour
Table 105 Subaddresses F9H and FAH DATA BYTE XCP horizontal cursor position DESCRIPTION
Table 106 Subaddress FAH DATA BYTE XHS horizontal hot spot of cursor DESCRIPTION
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Philips Semiconductors
Product specification
Digital video encoder
Table 107 Subaddresses FBH and FCH DATA BYTE YCP vertical cursor position DESCRIPTION
SAA7104E; SAA7105E
Table 108 Subaddress FCH DATA BYTE YHS vertical hot spot of cursor DESCRIPTION
Table 109 Subaddress FDH DATA BYTE LUTOFF CMODE LUTL IF LOGIC LEVEL 0 1 0 1 0 1 0 1 2 3 4 5 6 MATOFF DFOFF 0 1 0 1 colour look-up table is active colour look-up table is bypassed cursor mode; input colour will be inverted auxiliary cursor colour will be inserted LUT loading via input data stream is inactive colour and cursor LUTs are loaded via input data stream input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR input format is 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB input format is 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB input format is 8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR input format is 8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock) (in subaddresses 91H and 94H set XPIX = number of active pixels/line) input format is 8-bit non-interlaced index colour input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR (special bit ordering) RGB to CR-Y-CB matrix is active RGB to CR-Y-CB matrix is bypassed down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active down formatter is bypassed DESCRIPTION
Table 110 Subaddress FEH DATA BYTE CURSA DESCRIPTION RAM start address for cursor bit map; the byte following subaddress FEH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
Table 111 Subaddress FFH DATA BYTE COLSA DESCRIPTION RAM start address for colour LUT; the byte following subaddress FFH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition
In subaddresses 5BH, 5CH, 5DH, 5EH, 62H and D3H all IRE values are rounded up. 2004 Mar 04 48
Philips Semiconductors
Product specification
Digital video encoder
7.25 Slave transmitter
SAA7104E; SAA7105E
Table 112 Slave transmitter (slave address 89H) REGISTER FUNCTION Status byte Chip ID FIFO status DATA BYTE SUBADDRESS D7 00H 1CH 80H VER2 CID7 0 D6 VER1 CID6 0 D5 VER0 CID5 0 D4 CCRDO CID4 0 D3 CCRDE CID3 0 D2 0 CID2 0 D1 FSEQ CID1 OVFL D0 O_E CID0 UDFL
Table 113 Subaddress 00H DATA BYTE VER CCRDO LOGIC LEVEL - 1 0 CCRDE 1 0 FSEQ O_E 1 0 1 0 Table 114 Subaddress 1CH DATA BYTE CID DESCRIPTION chip ID of SAA7104E = 04H; chip ID of SAA7105E = 05H DESCRIPTION version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 101 binary Closed Caption bytes of the odd field have been encoded the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded Closed Caption bytes of the even field have been encoded the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields) not first field of a sequence during even field during odd field
Table 115 Subaddress 80H DATA BYTE IFERR BFERR OVFL UDFL LOGIC LEVEL 0 1 0 1 0 1 0 1 normal FIFO state input FIFO overflow/underflow has occurred normal FIFO state buffer FIFO overflow, only if YUPSC = 1 no FIFO overflow FIFO overflow has occurred; this bit is reset after this subaddress has been read no FIFO underflow FIFO underflow has occurred; this bit is reset after this subaddress has been read DESCRIPTION
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 (1) SCBW = 1. (2) SCBW = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.4 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.5 Chrominance transfer characteristic 2.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
Gv handbook, full pagewidth (dB) 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 0 (1) (2) (3) (4) 2 4 6 8 10 12 f (MHz) CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. 14
(4) (2) (3) (1)
6
MGD672
Fig.6 Luminance transfer characteristic 1 (excluding scaler).
handbook, halfpage
MBE736
1
Gv (dB) 0
(1)
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
(1) CCRS1 = 0; CCRS0 = 0
Fig.7 Luminance transfer characteristic 2 (excluding scaler).
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
handbook, full pagewidth
Gv 6 0
MGB708
(dB)
-6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
Fig.8 Luminance transfer characteristic in RGB (excluding scaler).
handbook, full pagewidth
Gv 6 0
MGB706
(dB)
-6 -12 -18 -24 -30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
Fig.9 Colour difference transfer characteristic in RGB (excluding scaler).
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Philips Semiconductors
Product specification
Digital video encoder
8 BOUNDARY SCAN TEST
SAA7104E; SAA7105E
The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 116. Details about the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) of the SAA7104E; SAA7105E is available on request.
The SAA7104E; SAA7105E has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7104E; SAA7105E follows the "IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO).
Table 116 BST instructions supported by the SAA7104E; SAA7105E INSTRUCTION BYPASS EXTEST SAMPLE DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. This optional instruction allows testing of the internal logic (no support for customer available). This private instruction allows testing by the manufacturer (no support for customer available). When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.10.
CLAMP IDCODE INTEST USER1 8.1
Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW. 8.2 Device identification codes
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during field service.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
handbook, full pagewidth
MSB 31 TDI 28 27 0111000100000100 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1
LSB 0 1 TDO
0101
4-bit version code
MHC568
a. SAA7104E.
LSB
handbook, full pagewidth
MSB 31 TDI 28 27 0111000100000101 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1
0 1 TDO
0101
4-bit version code
MHC569
b. SAA7105E. Fig.10 32 bits of identification code.
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and grounded (0 V); all supply pins connected together. SYMBOL VDDD VDDA Vi(A) Vi(n) Vi(D) PARAMETER digital supply voltage analog supply voltage input voltage at analog inputs input voltage at pins XTALI, SDA and SCL input voltage at digital inputs or I/O pins outputs in 3-state outputs in 3-state; note 1 VSS Tstg Tamb Vesd voltage difference between VSSA(n) and VSSD(n) storage temperature ambient temperature electrostatic discharge voltage CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 - -65 0 human body model; - note 2 machine model; note 3 Notes 1. Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V. 2. Class 2 according to EIA/JESD22-114-B. 3. Class B according to EIA/JESD22-115-A. - MAX. +4.6 +4.6 +4.6 VDDD + 0.5 +4.6 +5.5 100 +150 70 2000 200 V V V V V V mV C C V V UNIT
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Philips Semiconductors
Product specification
Digital video encoder
10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Note PARAMETER thermal resistance from junction to ambient CONDITIONS in free air
SAA7104E; SAA7105E
VALUE 38(1)
UNIT K/W
1. The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample copper area direct under the SAA7104E; SAA7105E with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended. 11 CHARACTERISTICS Tamb = 0 to 70 C (typical values excluded); unless otherwise specified. SYMBOL Supplies VDDA VDDD2, VDDD3, VDDD4 VDDD1 analog supply voltage digital supply voltage 3.15 3.15 3.3 3.3 3.45 3.45 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
digital supply voltage (DVO)
1.045 1.425 1.71 2.375 3.135
1.1 1.5 1.8 2.5 3.3 110 175 - - -
1.155 1.575 1.89 2.625 3.465 115 200
V V V V V mA mA
IDDA IDDD Inputs VIL
analog supply current digital supply current
note 1 note 2
1 1 -0.1 -0.5 -0.5
LOW-level input voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDDD1 = 3.3 V; note 3 pins RESET, TMS, TCK, TRST and TDI
+0.2 +0.8 +0.8
V V V
VIH
HIGH-level input voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDDD1 = 3.3 V; note 3 pins RESET, TMS, TCK, TRST and TDI
VDDD1 - 0.2 - 2 2 - - - - - - -
VDDD1 + 0.1 V VDDD1 + 0.3 V VDDD2 + 0.3 V 10 10 10 10 A pF pF pF
ILI Ci
input leakage current input capacitance clocks data I/Os at high-impedance
- - -
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
SYMBOL Outputs VOL
PARAMETER
CONDITIONS
MIN.
TYP. - - -
MAX.
UNIT
LOW-level output voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDDD1 = 3.3 V; note 3 pins TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC
0 0 0
0.1 0.4 0.4
V V V
VOH
HIGH-level output voltage
VDDD1 = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDDD1 = 3.3 V; note 3 pins TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC
VDDD1 - 0.1 - 2.4 2.4 - -
VDDD1 VDDD1 VDDD2
V V V
I2C-bus; pins SDA and SCL VIL VIH Ii VOL Io TPIXCLK td(CLKD) tr tf Input timing tSU;DAT tHD;DAT tSU;DAT tHD;DAT input data set-up time input data hold time input data set-up time input data hold time pins PD11 to PD0 pins PD11 to PD0 pins HSVGC, VSVGC and FSVGC; note 6 pins HSVGC, VSVGC and FSVGC; note 6 2 0.9 2 1.5 - - - - - - - - ns ns ns ns LOW-level input voltage HIGH-level input voltage input current LOW-level output voltage (pin SDA) output current Vi = LOW or HIGH IOL = 3 mA during acknowledge -0.5 0.7VDDD2 -10 - 3 - - - - - - - 50 50 - - 0.3VDDD2 +10 0.4 - - - 60 60 1.5 1.5 V A V mA VDDD2 + 0.3 V
Clock timing; pins PIXCLKI and PIXCLKO cycle time delay from PIXCLKO to PIXCLKI duty factor tHIGH/TPIXCLK duty factor tHIGH/TCLKO2 rise time fall time note 4 note 5 note 4 output note 4 note 4 12 - 40 40 - - ns ns % % ns ns
Crystal oscillator fnom f/fnom nominal frequency permissible deviation of nominal frequency note 7 - -50 27 - - +50 MHz 10-6
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - 1.5 3.5 - - - -
MAX.
UNIT C pF fF pF
CRYSTAL SPECIFICATION Tamb CL RS C1 C0 Co(L) to(h)(gfx) to(d)(gfx) to(h) ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 0 8 - 1.2 2.8 70 - 80 1.8 4.2
Data and reference signal output timing output load capacitance output hold time to graphics controller output delay time to graphics controller output hold time pins HSVGC, VSVGC, FSVGC and CBO pins HSVGC, VSVGC, FSVGC and CBO pins TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC pins TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC 8 1.5 - 3 40 - 10 - pF ns ns ns
to(d)
output delay time
-
-
25
ns
CVBS and RGB outputs Vo(CVBS)(p-p) output voltage CVBS (peak-to-peak value) Vo(VBS)(p-p) Vo(C)(p-p) Vo(RGB)(p-p) Vo Ro(L) BDAC ILElf(DAC) DLElf(DAC) output voltage VBS (S-video) (peak-to-peak value) output voltage C (S-video) (peak-to-peak value) output voltage R, G, B (peak-to-peak value) inequality of output signal voltages output load resistance output signal bandwidth of DACs low frequency integral linearity error of DACs low frequency differential linearity error of DACs -3 dB; note 8 see Table 117 see Table 117 see Table 117 see Table 117 - - - - - - - - - 1.23 1 0.89 0.7 2 37.5 170 - - - - - - - - - 3 1 V V V V % MHz LSB LSB
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Philips Semiconductors
Product specification
Digital video encoder
Notes 1. Minimum value for I2C-bus bit DOWNA = 1. 2. Minimum value for I2C-bus bit DOWND = 1.
SAA7104E; SAA7105E
3. Levels refer to pins PD11 to PD0, FSVGC, PIXCLKI, VSVGC, PIXCLKO, CBO, TVD, and HSVGC, being inputs or outputs directly connected to a graphics controller. Input sensitivity is 1/2VDDD2 + 100 mV for HIGH and 1/2VDDD2 - 100 mV for LOW. The reference voltage 1/2VDDD2 is generated on chip. 4. The data is for both input and output direction. 5. This parameter is arbitrary, if PIXCLKI is looped through the VGC. 6. Tested with programming IFBP = 1. 7. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 8. 1 B -3 dB = ------------------------------------------------ with RL = 37.5 and Cext = 20 pF (typical). 2R L ( C ext + 5 pF )
handbook, full pagewidth
TPIXCLK tHIGH VOH 0.5VDDD1 VOL td(CLKD) tf tr VIH
PIXCLKO
PIXCLKI
0.5VDDD1 VIL tHD;DAT tSU;DAT tHD;DAT tSU;DAT VIH
PDn VIL to(d) to(h) any output VOL
MHC567
VOH
Fig.11 Input/output timing specification.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
handbook, full pagewidth
HSVGC
CBO
PD XOFS IDEL XPIX HLEN
MHB905
Fig.12 Horizontal input timing.
handbook, full pagewidth
HSVGC
VSVGC
CBO YOFS YPIX
MHB906
Fig.13 Vertical input timing.
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Philips Semiconductors
Product specification
Digital video encoder
11.1 Teletext timing
SAA7104E; SAA7105E
Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. It is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct I2C-bus register settings.
Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 s (PAL) or tTTX = 10.5 s (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse.
handbook, full pagewidth
CVBS/Y t TTX text bit #: TTX_SRES t PD TTXRQ_XCLKO2
MHB891
t i(TTXW) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
t FD
Fig.14 Teletext timing.
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Philips Semiconductors
Product specification
Digital video encoder
12 APPLICATION INFORMATION
SAA7104E; SAA7105E
DVO handbook, full pagewidth supply 0.1 F DGND
+3.3 V digital supply 0.1 F
AGND 1 nF DGND 10 pF 0.1 H 27 MHz
+3.3 V analog supply 0.1 F 10 pF AGND use one capacitor for each VDDA XTALO VDDA1 to VDDA3 VSM, HSM_CSYNC
use one capacitor for each VDDD VDDD1 VDDD2 to VDDD4
XTALI
GREEN_VBS_CVBS FLTR0 75 75 UY
AGND
AGND
AGND
RED_CR_C_CVBS digital inputs and outputs
SAA7104E SAA7105E
75
FLTR1 75 UC
AGND
AGND
AGND
BLUE_CB_CVBS FLTR2 75 75 UCVBS
AGND VSSD1 to VSSD4 VSSA RSET 1 k DUMP 12
AGND
AGND
DGND
AGND
AGND
AGND
MHC574
Fig.15 Application circuit.
2004 Mar 04
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
handbook, halfpage
C16 120 pF L2 2.7 H C10 390 pF L3 2.7 H C13 560 pF
AGND
JP11 FIN
JP12 FOUT
FILTER 1 = byp. ll act.
MHB912
Fig.16 FLTR0, FLTR1 and FLTR2 of Fig.15.
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Philips Semiconductors
Product specification
Digital video encoder
SAA7104E; SAA7105E
handbook, full pagewidth
SAA7104E SAA7105E
A5 XTALI 27.00 MHz A6 XTALO A5
SAA7104E SAA7105E
A6 XTALO 27.00 MHz XTALI
4.7 H 1 nF
18 pF
18 pF
39 pF
39 pF
MHC570
(1a) With 3rd-harmonic quartz. Crystal load = 8 pF.
(1b) With fundamental quartz. Crystal load = 20 pF.
handbook, full pagewidth
SAA7104E SAA7105E
A5 XTALI 27.00 MHz n.c. clock A6 XTALO A5
SAA7104E SAA7105E
A6 XTALO Rs XTALI
MHC571
(2a) With direct clock.
(2b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high, a resistance Rs can be placed in series with the oscillator output XTALO. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease.
Fig.17 Oscillator application.
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Philips Semiconductors
Product specification
Digital video encoder
12.1 Reconstruction filter
SAA7104E; SAA7105E
Tables 41 to 48 for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 117 for a 100100 colour bar signal. By setting the reference currents of the DACs as shown in Table 117, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16H, parameter DACF = 0000b, that means the fine adjustment for all DACs in common is set to 0%. If S-video output is desired, the adjustment for the C (chrominance subcarrier) output should be identical to the one for VBS (luminance plus sync) output.
Figure 16 shows a possible reconstruction filter for the digital-to-analog converters. Due to its cut-off frequency of 6 MHz, it is not suitable for HDTV applications. 12.2 Analog output voltages
The analog output voltages are dependent on the total load (typical value 37.5 ), the digital gain parameters and the I2C-bus settings of the DAC reference currents (analog settings). The digital output signals in front of the DACs under nominal (nominal here stands for the settings given in Table 117 Digital output signals conversion range SET/OUT Digital settings Digital output Analog settings Analog output 12.3
CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE see Tables 41 to 48 1014 e.g. B DAC = 1FH 1.23 V (p-p) see Tables 41 to 48 881 e.g. G DAC = 1BH 1.00 V (p-p)
RGB, BLACK-TO-WHITE see Table 36 876 e.g. R DAC = G DAC = B DAC = 0BH 0.70 V (p-p)
Suggestions for a board layout
Use separate ground planes for analog and digital ground. Connect these planes only at one point directly under the device, by using a 0 resistor directly at the supply stage. Use separate supply lines for analog and digital supply. Place the supply decoupling capacitors close to the supply pins. Use Lbead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (EMC).
Place the analog coupling (clamp) capacitors close to the analog input pins. Place the analog termination resistors close to the coupling capacitors. Be careful of hidden layout capacitors around the crystal application. Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy.
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Philips Semiconductors
Product specification
Digital video encoder
13 PACKAGE OUTLINE
BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm
D D1 B A
SAA7104E; SAA7105E
SOT472-1
ball A1 index area A E1 E A1 detail X A2
C e1 e P N M L K J H G F E D C B A shape optional (4x) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.75 A1 0.5 0.3 A2 1.25 1.05 b 0.6 0.4 D 15.2 14.8 D1 13.7 13.0 E 15.2 14.8 E1 13.7 13.0 e 1 e1 13 e2 13 v 0.3 w 0.1 y 0.15 y1 0.35 10 mm X
1/2 e
b
v M C A B w M C
y1 C
y
e
e2
1/2 e
OUTLINE VERSION SOT472-1
REFERENCES IEC 144E JEDEC MS-034 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 00-03-04 03-01-22
2004 Mar 04
65
Philips Semiconductors
Product specification
Digital video encoder
14 SOLDERING 14.1 Introduction to soldering surface mount packages
SAA7104E; SAA7105E
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON-T and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
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Philips Semiconductors
Product specification
Digital video encoder
14.5
SAA7104E; SAA7105E
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes
not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7)
not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Mar 04
67
Philips Semiconductors
Product specification
Digital video encoder
15 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
SAA7104E; SAA7105E
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Mar 04
68
Philips Semiconductors
Product specification
Digital video encoder
18 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7104E; SAA7105E
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2004 Mar 04
69
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R21/01/pp70
Date of release: 2004
Mar 04
Document order number:
9397 750 11436

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